1. Field of the Invention
The present invention relates to a communication system, and in particular, to a CMOS radio frequency (RF) communication system.
2. Background of the Related Art
Presently, a radio frequency (RF) communications system has a variety of applications including PCS communication and IMT systems. As such, a CMOS chip integration of the system has been pursued to reduce the cost, size and power consumption.
Generally, the RF communication system is composed of RF front-end block and base-band digital signal processing DSP) block or baseband modem block. Currently, the base-band DSP block can be implemented with low cost and low power CMOS technology. However, the RF front-end cannot be implemented by CMOS technology because of limitations in speed, bandwidth and noise characteristics, which are below the speed, the frequency and noise specifications of popular RF communication systems.
For example, the PCS hand-phone systems operate at a frequency over 2.0 GHz, but current CMOS technology reliably operates only up to approximately 1.0 GHz in terms of speed and noise. Hence, the RF front-end block is implemented using bipolar, bi-CMOS or GaAs technology that has better speed, bandwidth and noise characteristics than CMOS technology but is more expensive and consumes more power.
Currently, two different types of RF architecture called xe2x80x9cdirect conversionxe2x80x9d and super-heterodyne (double conversion) are used for CMOS RF communication systems. Both architectures have advantages and disadvantages in terms of CMOS implementations.
FIG. 1 is a diagram showing a related art direct conversion RF system 100. A related art direct conversion CMOS RF communication system 100 includes an antenna 105, a RF filter 110, a low noise amplifier (LNA) 120, a phase-locked loop (PLL) 130, a first mixer 140, a second mixer 142, first and second amplifiers 150, 152, a first low pass filter (LPF) 160, a second LPF 162, first and second variable gain amplifiers (VGA) 170, 172 each including automatic gain control (AGC) loops, a first analog/digital (A/D) converter 180, a second A/D converter 182, a third mixer 190 and a power amplifier 192.
The antenna 105 receives RF signals. The received RF signal is composed of various RF bands. Selected RF signals are then filtered at the RF filter 110. That is, out-of-band RF signals (e.g., irrelevant RF bands) are removed by the RF filter 110. The filtered in-band RF signals are amplified with a gain at the LNA 120. However, the in-band RF signal is composed of in-band channels and possible image bands, which is shown as A in FIGS. 1 and 2. The in-band RF signals passing through the LNA 120 are directly demodulated into base band signals by quadrature multiplication at the first and second mixers 140 and 142 because the LO frequency is equal to the carrier frequency. The PLL 130 preferably generates two types of clock signals, I clock signals and Q clock signals using a voltage controlled oscillator (VCO). The I clock signals and the Q clock signals are the same excepting a phase difference. The I signals preferably have a phase difference of 90 degrees from the Q signals. That is, Q signals are phase shifted with respect to quadrature phase shift I signals. The two sets of signals I and Q are preferably used to increase the ability of the RF system to identify or maintain received information regardless of noise and interference. Sending two types of signals having different phases reduces the probability of information loss or change.
As shown at B in FIGS. 1 and 2, the down converted signal includes the desired channel, adjacent channels and an up-converted signal. The down-converted signal is amplified by amplifiers 150, 152 before passing through corresponding low-pass filters (LPF) 160, 162 to prevent drastic signal-to-noise-ratio (SNR) degradation by noise injection from the LPFs 160, 162, which is shown as C in FIGS. 1 and 2. The signals from the LPFs 160, 162 are amplified by variable gain amplifiers (VGAs) 170, 172, respectively and become respective signals required for A/D conversion at first and second A/D converters 180, 182. However, the desired channel cannot be amplified to a maximum level allowed by the linearity limit because the adjacent channel can reach the linearity limit before the desired channel is amplified to the required level. Thus, in the related art direct conversion architecture 100, amplification of the entire channel is reduced as the adjacent channel power increases, which also results in SNR degradation. As shown at D in FIGS. 1 and 2, the LPFs 160, 162 output a large noise floor that is added to the desired channel by the LPFs 160, 162. Accordingly, both the desired channel and the noise floor are amplified when the desired channel is amplified to the required level before the A/D conversion as shown at E in FIGS. 1 and 2.
The digital signals are then transferred to a base-band discrete-time signal processing (DSP) block (not shown). Channel selection is performed by changing frequency f0 in at the phase-locked loop (PLL) 130.
As described above, the related art direct conversion RF system 100 has advantages for CMOS RF integration because of its simplicity. In the related art direct conversion RF system only a single PLL is required. Further, in the related art direct conversion RF system high-quality filters are not required. However, the related art direct conversion architecture has disadvantages that make single chip integration difficult or impossible. As shown in FIG. 3A, clock signals cos xcfx89LOt from a local oscillator (LO) such as the VCO may leak to either the mixer input or to the antenna where radiations can occur because the local oscillator (LO) is at the same frequency as the RF carriers. The unintentionally transmitted clock signals xcex94(t)cos xcfx89LOt can reflect off nearby objects and be xe2x80x9cre-receivedxe2x80x9d by the mixer again. The low pass filter outputs a signal M(t)+xcex94(t) because of leakages of clock signals. As shown in FIG. 3B, self-mixing with the local oscillator results in problems such as time variations or xe2x80x9cwanderingxe2x80x9d DC-offsets at the output of the mixer. The time-varying DC-offset together with inherent circuit offsets significantly reduce the dynamic range of the receiver portion. Further, as discussed above, a related art direct conversion RF system requires a high-frequency, low-phasenoise PLL for channel selection, which is difficult to achieve with an integrated CMOS voltage controlled oscillator (VCO).
FIG. 4 shows a block diagram of a related art RF communication system 400 according to a double conversion architecture that considers all of the potential channels and frequency translates them first from RF to IF and then from IF to baseband using a tunable channel select PLL. As shown in FIG. 4, the RF communication system 400 includes antenna 405, a RF filter 410, a LNA 420, IR filter 425, a phase lock loop (PLL) PLL1430, a first mixer 435, a IF filter 440, IF VGA 450, a PLL2460, a second mixer 465, a LPF 470, an A/D converter 480, a third mixer 490 and a power amplifier 492.
The mixers 435, 465 are all for demodulation while the mixer 490 is for modulation. The mixer 435 is for a selected RF frequency and the mixer 465 is for an intermediate frequency (IF). The PLL1430 generates clock signals at a high frequency or the RF frequency, the PLL2460 generates clock signals having a low frequency or the intermediate frequency (IF).
Transmission data are multiplied with the clock signals having the high frequency from the PLL 430 to have an original transmission data frequency by the mixer 490. The output signals of the mixer 490 are amplified with a gain at the power amplifier 492 and then radiated through the antenna 405 for transmission.
Operations of the related art super-heterodyne receiver will now be described. Initially, an RF signal is received by the antenna 405. The received RF signal includes various RF bands. The RF filter 410 filters out out-of-band RF signals and the LNA 420 amplifies the in-band RF signal composed of in-band signals and possible image bands as shown at A in FIGS. 4-5. Image bands are filtered out by the image rejection (4R) filter 425 as shown at B in FIGS. 4-5. Otherwise, the image bands are mixed with the in-band RF signal after a first down conversion by the mixer 435 and PLL1430 combination. Thus, the in-band RF channels are down converted into an IF frequency by a first down conversion at mixer 435 using a local oscillator signal LO1 as shown at C in FIGS. 4-5. The PLL1430 generates the local oscillator signals for I signals of the RF signals and for Q signals of the RF signals.
The band-pass IF filter 440 rejects adjacent channels so that only the desired or dedicated channel has a dominant power level at the IF frequency as shown at D in FIGS. 4-5. The IF VGA 450 that includes an AGC loop amplifies the dedicated channel at the IF frequency to get an amplitude sufficiently large to overcome a large noise floor of the downstream LPF 470. The AGC loop continuously detects the amplitude of the IF VGA 450 output and controls its VGA gain so that a maximum amplitude allowed by the linearity limit can be obtained. As a result, the dual-conversion receiver can achieve the required SNR by the IF-filtering and amplification as shown at E in FIGS. 4-5. An adjacent channel is not a bottleneck or problem of IF amplification because of filtering by IF filter 440 before the IF amplification is performed by the IF VGA 450. However, if the adjacent channel is not eliminated before the IF amplification, the dedicated channels cannot be amplified to a maximum value because the adjacent channel can reach the linearity limit before the dedicated channel is amplified to the maximum level.
The amplified RF signal is down-converted again into the baseband by the second down-converting mixer 465 and using a local oscillator signal LO2 from the PLL2460 as shown at F in FIGS. 4-5. The low-pass filter 470 filters out the up-converted signal and remaining adjacent channels as shown at G in FIGS. 4-5, which indicates the noise floor added by the LPF 470. The A/D converter 480 converts the signals into digital data, which is then transferred into a baseband discrete-time signal processing ASP) block (not shown). All of the channels at the IF stage are frequency-translated directly to baseband frequency by the tunable PLL2460 for channel selection.
As described above, the related art super-heterodyne RF system 400 has various advantages. The related art double conversion RF system 400 performs the channel tuning using the lower-frequency (i.e., IF) second PLL 460, but not the high-frequency, (i.e., RF) first PLL 430. Consequently, the high-frequency RF PLL 430 can be a fixed-frequency PLL that can be more effectively optimized. Further, since channel tuning is performed with the IF PLL 460, which operates at a lower frequency, the contribution of phase noise into channel selection can be reduced. However, the related art double conversion RF system 400 has various disadvantages to overcome for single chip integration. The related art double conversion RF system 300 uses two PLLs, which are difficult to integrate in a single chip. Further, the frequency of first PLL remains too high to be implemented with CMOS technology, and in particular, with a CMOS VCO. In addition, self-mixing problem still occurs because the second PLL is at the same frequency of the IF desired carrier. The output signals of the second mixer may leak to a substrate or may leak to the second mixer again. The time-varying DC-offset, together with inherent circuit offsets significantly reduces the dynamic range of the receiver portion. In addition, CMOS integration of an IR filter and an IF filter is very difficult or impossible.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the present invention is to provide a single chip CMOS transmitter/receiver and method that substantially obviates one or more problems and disadvantages of the related art.
A further object of the present invention is to fabricate a CMOS RF front end and method for using same that allows one chip integration of an RF communication system.
Another object of the present invention is to provide an RF communication system and method with reduced cost and power requirements.
Still another object of the present invention is to provide a reliable high speed, low noise CMOS RF communication system and method for using same.
Another object of the present invention is to increase a frequency range of a RF front end of an RF communication system.
Another object of the present invention is to provide a direct conversion RF communication system and method that provides a prescribed SNR regardless of an adjacent channel power level.
Another object of the present invention is to provide a baseband structure for a CMOS RF receiver on a single chip using selective two step amplification to meet desired gain for a selected RF channel and remove a larger adjacent channel.
To achieve at least the above objects and advantages in whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a direct conversion communication system that includes a receiver unit that receives signals including selected signals having a carrier frequency, a demodulation-mixer that mixes the received carrier frequency selected signals and that outputs baseband selected signals, and a baseband amplification circuit that includes first and second stage AGC amplifiers that receive the baseband selected signals and that selectively amplify in-channel signals to a prescribed amplitude.
To further achieve the objects in whole or in part, and in accordance with the purpose of the present invention, there is provided a single chip RF communication system, that includes a transceiver that receives and transmits RF signals, a PLL for generating a plurality of 2N-phase clock signals having a substantially identical frequency 2*f0/N, wherein f0 is the carrier frequency, and wherein N is a positive integer, a demodulation mixer that mixes the RF signals from the transceiver with the plurality of 2N-phase clock signals from the PLL to output RF signals having a frequency reduced relative to the carrier frequency f0, wherein the demodulation mixer comprises a plurality of two input mixers, an AGC loop coupled to the demodulation-mixer, a gain-merged filter coupled to the AGC loop, and an A/D converting unit coupled to the gain-merged filter that converts the RF signals from the demodulation mixer into digital signals.
To further achieve the objects of the invention, in whole or in part, and in accordance with the purpose of the present invention, there is provided a method of operating a RF communication system that includes receiving signals including selected signals having a carrier frequency, generating more than two multi-phase clock signals having a substantially identical frequency different from the carrier frequency, mixing the received selected signals with the more than two multi-phase clock signals to output demodulated selected signals having a frequency reduced from the carrier frequency, wherein several of the more than two multi-phase clock signals are mixed to demodulate one of a first carrier frequency signal and a second carrier frequency signal, amplifying the demodulated selected signals until one of a selected channel and an adjacent channel reach a linearity limit and amplifying and filtering the adjacent channel and amplifying the selected channel to a desired dynamic range.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.